Altium

Design Rule Verification Report

Date:		04.08.2018
Time:		09:46:48
Elapsed Time:		00:00:12
Filename:		T:\prjbluetechnix\Melexis\MLX75123-Eval\phase3_development\hardware\EVK75123-Sensor-MLX75024\layout\EVK75123-MLX75024.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.4mm) (InPolygon),(InPadClass('MH'))	0
Clearance Constraint (Gap=0.23mm) (All),(not PadIsPlated)	0
Clearance Constraint (Gap=0.1mm) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.1mm) (Max=3mm) (Preferred=0.15mm) (All)	0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.1mm) (Prefered=0.1mm) and Width Constraints (Min=0.12mm) (Max=0.12mm) (Prefered=0.12mm) (InNetClass('DIFF100'))	0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.12mm) (Max=0.12mm) (Prefered=0.12mm) and Width Constraints (Min=0.1mm) (Max=0.1mm) (Prefered=0.1mm) (InDifferentialPair ('D'))	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.5mm) (Conductor Width=0.3mm) (Air Gap=0.2mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.1mm) (Max=4mm) (All)	0
Pads and Vias to follow the Drill pairs settings	0
Hole To Hole Clearance (Gap=0.15mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(IsVia)	0
Net Antennae (Tolerance=0mm) (All)	0
Matched Lengths(Tolerance=25.4mm) (InDifferentialPair ('DDR.CLK'))	0
Vias Under SMD Constraint (Allowed=Allowed) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	0