Altium

Design Rule Verification Report

Date:		14.04.2017
Time:		14:32:09
Elapsed Time:		00:00:03
Filename:		T:\prjbluetechnix\Melexis\MLX75123-Eval\phase3_development\hardware\EVK75123-Interface\layout\EVK75123-Interface.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.15mm) (All),(All)	0
Clearance Constraint (Gap=0.127mm) (IsStitchingVia and InNet('GND')),((IsVia and (Not IsStitchingVia)) Or IsPad)	0
Clearance Constraint (Gap=0.15mm) (InNetClass('GETH')),(All)	0
Clearance Constraint (Gap=0.2mm) (All),(not PadIsPlated)	0
Clearance Constraint (Gap=0.1mm) (isvia),(ispad and not InPadClass('EP'))	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=0.15mm) (Max=3mm) (Preferred=0.15mm) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.5mm) (Conductor Width=0.3mm) (Air Gap=0.2mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.3mm) (Max=3.8mm) (All)	0
Pads and Vias to follow the Drill pairs settings	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(IsVia)	0
Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)	0
Net Antennae (Tolerance=0mm) (All)	0
Matched Lengths(Tolerance=0.2mm) (InxSignalClass('MIPI'))	0
Matched Lengths(Tolerance=0.2mm) (InxSignalClass('All xSignals'))	0
Height Constraint (Min=0mm) (Max=100mm) (Prefered=12.7mm) (All)	0
Total	0