#include "usb_conf.h"Defines | |
| #define | REGADDRPTR (0x00*OFFSET_MULTIPLIER) |
| #define | REGDATA (0x01*OFFSET_MULTIPLIER) |
| #define | IRQSTAT0 (0x02*OFFSET_MULTIPLIER) |
| #define | ENDPOINT_0_INTERRUPT 0 |
| #define | ENDPOINT_A_INTERRUPT 1 |
| #define | ENDPOINT_B_INTERRUPT 2 |
| #define | ENDPOINT_C_INTERRUPT 3 |
| #define | VIRTUALIZED_ENDPOINT_INTERRUPT 4 |
| #define | SETUP_PACKET_INTERRUPT 5 |
| #define | DMA_DONE_INTERRUPT 6 |
| #define | SOF_INTERRUPT 7 |
| #define | IRQSTAT1 (0x03*OFFSET_MULTIPLIER) |
| #define | CONTROL_STATUS_INTERRUPT 1 |
| #define | VBUS_INTERRUPT 2 |
| #define | SUSPEND_REQUEST_INTERRUPT 3 |
| #define | SUSPEND_REQUEST_CHANGE_INTERRUPT 4 |
| #define | RESUME_INTERRUPT 5 |
| #define | ROOT_PORT_RESET_INTERRUPT 6 |
| #define | RESET_STATUS 7 |
| #define | PAGESEL (0x04*OFFSET_MULTIPLIER) |
| #define | DMAREQ (0x1c*OFFSET_MULTIPLIER) |
| #define | DMA_ENDPOINT_SELECT 0 |
| #define | DREQ_POLARITY 1 |
| #define | DACK_POLARITY 2 |
| #define | EOT_POLARITY 3 |
| #define | DMA_CONTROL_DACK 4 |
| #define | DMA_REQUEST_ENABLE 5 |
| #define | DMA_REQUEST 6 |
| #define | DMA_BUFFER_VALID 7 |
| #define | SCRATCH (0x1d*OFFSET_MULTIPLIER) |
| #define | IRQENB0 (0x20*OFFSET_MULTIPLIER) |
| #define | ENDPOINT_0_INTERRUPT_ENABLE 0 |
| #define | ENDPOINT_A_INTERRUPT_ENABLE 1 |
| #define | ENDPOINT_B_INTERRUPT_ENABLE 2 |
| #define | ENDPOINT_C_INTERRUPT_ENABLE 3 |
| #define | VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE 4 |
| #define | SETUP_PACKET_INTERRUPT_ENABLE 5 |
| #define | DMA_DONE_INTERRUPT_ENABLE 6 |
| #define | SOF_INTERRUPT_ENABLE 7 |
| #define | IRQENB1 (0x21*OFFSET_MULTIPLIER) |
| #define | CONTROL_STATUS_INTERRUPT_ENABLE 1 |
| #define | VBUS_INTERRUPT_ENABLE 2 |
| #define | SUSPEND_REQUEST_INTERRUPT_ENABLE 3 |
| #define | SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4 |
| #define | RESUME_INTERRUPT_ENABLE 5 |
| #define | ROOT_PORT_RESET_INTERRUPT_ENABLE 6 |
| #define | LOCCTL (0x22*OFFSET_MULTIPLIER) |
| #define | DATA_WIDTH 0 |
| #define | LOCAL_CLOCK_OUTPUT 1 |
| #define | DMA_SPLIT_BUS_MODE 4 |
| #define | BYTE_SWAP 5 |
| #define | BUFFER_CONFIGURATION 6 |
| #define | LOCAL_CLOCK_OUTPUT_OFF 0 |
| #define | LOCAL_CLOCK_OUTPUT_3_75MHZ 1 |
| #define | LOCAL_CLOCK_OUTPUT_7_5MHZ 2 |
| #define | LOCAL_CLOCK_OUTPUT_15MHZ 3 |
| #define | LOCAL_CLOCK_OUTPUT_30MHZ 4 |
| #define | LOCAL_CLOCK_OUTPUT_60MHZ 5 |
| #define | BUFFER_CONFIGURATION_EPA512_EPB512 0 |
| #define | BUFFER_CONFIGURATION_EPA1024_EPB512 1 |
| #define | BUFFER_CONFIGURATION_EPA1024_EPB1024 2 |
| #define | BUFFER_CONFIGURATION_EPA1024DB 3 |
| #define | CHIPREV_LEGACY (0x23*OFFSET_MULTIPLIER) |
| #define | NET2270_LEGACY_REV 0x40 |
| #define | LOCCTL1 (0x24*OFFSET_MULTIPLIER) |
| #define | DMA_DACK_ENABLE 2 |
| #define | SLOW_DREQ 0 |
| #define | FAST_DREQ 1 |
| #define | BURST_MODE 2 |
| #define | CHIPREV_2272 (0x25*OFFSET_MULTIPLIER) |
| #define | CHIPREV_NET2272_R1 0x10 |
| #define | CHIPREV_NET2272_R1A 0x11 |
| #define | USBCTL0 (0x18*OFFSET_MULTIPLIER) |
| #define | IO_WAKEUP_ENABLE 1 |
| #define | USB_DETECT_ENABLE 3 |
| #define | USB_ROOT_PORT_WAKEUP_ENABLE 5 |
| #define | USBCTL1 (0x19*OFFSET_MULTIPLIER) |
| #define | VBUS_PIN 0 |
| #define | USB_FULL_SPEED 1 |
| #define | USB_HIGH_SPEED 2 |
| #define | GENERATE_RESUME 3 |
| #define | VIRTUAL_ENDPOINT_ENABLE 4 |
| #define | FRAME0 (0x1a*OFFSET_MULTIPLIER) |
| #define | FRAME1 (0x1b*OFFSET_MULTIPLIER) |
| #define | OURADDR (0x30*OFFSET_MULTIPLIER) |
| #define | FORCE_IMMEDIATE 7 |
| #define | USBDIAG (0x31*OFFSET_MULTIPLIER) |
| #define | FORCE_TRANSMIT_CRC_ERROR 0 |
| #define | PREVENT_TRANSMIT_BIT_STUFF 1 |
| #define | FORCE_RECEIVE_ERROR 2 |
| #define | FAST_TIMES 4 |
| #define | USBTEST (0x32*OFFSET_MULTIPLIER) |
| #define | TEST_MODE_SELECT 0 |
| #define | NORMAL_OPERATION 0 |
| #define | TEST_J 1 |
| #define | TEST_K 2 |
| #define | TEST_SE0_NAK 3 |
| #define | TEST_PACKET 4 |
| #define | TEST_FORCE_ENABLE 5 |
| #define | XCVRDIAG (0x33*OFFSET_MULTIPLIER) |
| #define | FORCE_FULL_SPEED 2 |
| #define | FORCE_HIGH_SPEED 3 |
| #define | OPMODE 4 |
| #define | LINESTATE 6 |
| #define | NORMAL_OPERATION 0 |
| #define | NON_DRIVING 1 |
| #define | DISABLE_BITSTUFF_AND_NRZI_ENCODE 2 |
| #define | SE0_STATE 0 |
| #define | J_STATE 1 |
| #define | K_STATE 2 |
| #define | SE1_STATE 3 |
| #define | VIRTOUT0 (0x34*OFFSET_MULTIPLIER) |
| #define | VIRTOUT1 (0x35*OFFSET_MULTIPLIER) |
| #define | VIRTIN0 (0x36*OFFSET_MULTIPLIER) |
| #define | VIRTIN1 (0x37*OFFSET_MULTIPLIER) |
| #define | SETUP0 (0x40*OFFSET_MULTIPLIER) |
| #define | SETUP1 (0x41*OFFSET_MULTIPLIER) |
| #define | SETUP2 (0x42*OFFSET_MULTIPLIER) |
| #define | SETUP3 (0x43*OFFSET_MULTIPLIER) |
| #define | SETUP4 (0x44*OFFSET_MULTIPLIER) |
| #define | SETUP5 (0x45*OFFSET_MULTIPLIER) |
| #define | SETUP6 (0x46*OFFSET_MULTIPLIER) |
| #define | SETUP7 (0x47*OFFSET_MULTIPLIER) |
| #define | EP_DATA (0x05*OFFSET_MULTIPLIER) |
| #define | EP_STAT0 (0x06*OFFSET_MULTIPLIER) |
| #define | DATA_IN_TOKEN_INTERRUPT 0 |
| #define | DATA_OUT_TOKEN_INTERRUPT 1 |
| #define | DATA_PACKET_TRANSMITTED_INTERRUPT 2 |
| #define | DATA_PACKET_RECEIVED_INTERRUPT 3 |
| #define | SHORT_PACKET_TRANSFERRED_INTERRUPT 4 |
| #define | NAK_OUT_PACKETS 5 |
| #define | BUFFER_EMPTY 6 |
| #define | BUFFER_FULL 7 |
| #define | EP_STAT1 (0x07*OFFSET_MULTIPLIER) |
| #define | TIMEOUT 0 |
| #define | USB_OUT_ACK_SENT 1 |
| #define | USB_OUT_NAK_SENT 2 |
| #define | USB_IN_ACK_RCVD 3 |
| #define | USB_IN_NAK_SENT 4 |
| #define | USB_STALL_SENT 5 |
| #define | LOCAL_OUT_ZLP 6 |
| #define | BUFFER_FLUSH 7 |
| #define | EP_TRANSFER0 (0x08*OFFSET_MULTIPLIER) |
| #define | EP_TRANSFER1 (0x09*OFFSET_MULTIPLIER) |
| #define | EP_TRANSFER2 (0x0a*OFFSET_MULTIPLIER) |
| #define | EP_IRQENB (0x0b*OFFSET_MULTIPLIER) |
| #define | DATA_IN_TOKEN_INTERRUPT_ENABLE 0 |
| #define | DATA_OUT_TOKEN_INTERRUPT_ENABLE 1 |
| #define | DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 |
| #define | DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 |
| #define | SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 4 |
| #define | EP_AVAIL0 (0x0c*OFFSET_MULTIPLIER) |
| #define | EP_AVAIL1 (0x0d*OFFSET_MULTIPLIER) |
| #define | EP_RSPCLR (0x0e*OFFSET_MULTIPLIER) |
| #define | EP_RSPSET (0x0f*OFFSET_MULTIPLIER) |
| #define | ENDPOINT_HALT 0 |
| #define | ENDPOINT_TOGGLE 1 |
| #define | NAK_OUT_PACKETS_MODE 2 |
| #define | CONTROL_STATUS_PHASE_HANDSHAKE 3 |
| #define | INTERRUPT_MODE 4 |
| #define | AUTOVALIDATE 5 |
| #define | HIDE_STATUS_PHASE 6 |
| #define | ALT_NAK_OUT_PACKETS 7 |
| #define | EP_MAXPKT0 (0x28*OFFSET_MULTIPLIER) |
| #define | EP_MAXPKT1 (0x29*OFFSET_MULTIPLIER) |
| #define | ADDITIONAL_TRANSACTION_OPPORTUNITIES 3 |
| #define | NONE_ADDITIONAL_TRANSACTION 0 |
| #define | ONE_ADDITIONAL_TRANSACTION 1 |
| #define | TWO_ADDITIONAL_TRANSACTION 2 |
| #define | EP_CFG (0x2a*OFFSET_MULTIPLIER) |
| #define | ENDPOINT_NUMBER 0 |
| #define | ENDPOINT_DIRECTION 4 |
| #define | ENDPOINT_TYPE 5 |
| #define | ENDPOINT_ENABLE 7 |
| #define | EP_HBW (0x2b*OFFSET_MULTIPLIER) |
| #define | HIGH_BANDWIDTH_OUT_TRANSACTION_PID 0 |
| #define | DATA0_PID 0 |
| #define | DATA1_PID 1 |
| #define | DATA2_PID 2 |
| #define | MDATA_PID 3 |
| #define | EP_BUFF_STATES (0x2c*OFFSET_MULTIPLIER) |
| #define | BUFFER_A_STATE 0 |
| #define | BUFFER_B_STATE 2 |
| #define | BUFF_FREE 0 |
| #define | BUFF_VALID 1 |
| #define | BUFF_LCL 2 |
| #define | BUFF_USB 3 |
| #define | EP0_MAX_PACKET_SIZE 0x40 |
| #define | EPZERO ENDPOINT_0_INTERRUPT |
| #define | EPA ENDPOINT_A_INTERRUPT |
| #define | EPB ENDPOINT_B_INTERRUPT |
| #define | EPC ENDPOINT_C_INTERRUPT |
| #define | FIRST_PHYSICAL_ENDPOINT EPA |
| #define | LAST_PHYSICAL_ENDPOINT EPC |
| #define | PHYSICAL_ENDPOINT_COUNT (LAST_PHYSICAL_ENDPOINT + 1) |
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1.4.1