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Defines |
| #define | WLS_0 (0x0001 << 00) |
| | Bitpattern definitions for the Line Control Register (UART_LCR).
|
| #define | WLS_1 (0x0001 << 01) |
| #define | STOP_BIT (0x0001 << 02) |
| #define | PARITY_ENABLE (0x0001 << 03) |
| #define | EVEN_PARITY_SELECT (0x0001 << 04) |
| #define | STICK_PARITY (0x0001 << 05) |
| #define | SET_BREAK (0x0001 << 06) |
| #define | DLAB (0x0001 << 07) |
| #define | LOOP (0x0001 << 04) |
| | Bitpattern definitions for the Modem Control Register (UART_MCR).
|
| #define | DATA_READY (0x0001 << 00) |
| | Bitpattern definitions for the Line Status Register (UART_LSR).
|
| #define | OVERRUN_ERR (0x0001 << 01) |
| #define | PARITY_ERR (0x0001 << 02) |
| #define | FRAMEING_ERR (0x0001 << 03) |
| #define | BREAK_INT (0x0001 << 04) |
| #define | THR_EMPTY (0x0001 << 05) |
| #define | T_EMPTY (0x0001 << 06) |
| #define | ERBFI (0x0001 << 00) |
| | Bitpattern definitions for the Interrupt Enable Register (UART_IER).
|
| #define | ETBEI (0x0001 << 01) |
| #define | ELSI (0x0001 << 02) |
| #define | NINT (0x0001 << 00) |
| | Bitpattern definitions for the Interrupt Identification Register (UART_IIR).
|
| #define | STATUS_0 (0x0001 << 01) |
| #define | STATUS_1 (0x0001 << 02) |
| #define | UART_THR_EMPTY (0x0001 << 01) |
| | Bitpattern definitions for the Bitmasks for status bit pattern in (UART_IIR).
|
| #define | UART_RBR_FULL (0x0002 << 01) |
| #define | UART_LINE_STATUS (0x0003 << 01) |
| #define | CLOCK_ENABLE (0x0001 << 00) |
| | Bitpattern definitions for the Global Control Register (UART_GCTL).
|
| #define | IRDA_ENABLE (0x0001 << 01) |
| #define | RPOLC (0x0001 << 02) |
| #define | TPOLC (0x0001 << 03) |