#include <sys/exception.h>#include <services/services.h>#include <drivers/adi_dev.h>#include <services/adi_dcb.h>#include <services/adi_dma.h>#include <services/adi_int.h>#include <lwip/ADI_ETHER.h>#include "eth_conf.h"Defines | |
| #define | MSMC SMSC_BASE_ADDRESS |
| #define | ETH_ALEN 6 |
| #define | ETH_HLEN 14 |
| #define | ETH_ZLEN 60 |
| #define | ETH_DATA_LEN 1500 |
| #define | ETH_FRAME_LEN 1514 |
| #define | TCR_REG MSMC | 0x0000 |
| #define | TCR_TXENA 0x0001 |
| #define | TCR_LOOP 0x0002 |
| #define | TCR_FORCOL 0x0004 |
| #define | TCR_PAD_EN 0x0080 |
| #define | TCR_NOCRC 0x0100 |
| #define | TCR_MON_CSN 0x0400 |
| #define | TCR_FDUPLX 0x0800 |
| #define | TCR_STP_SQET 0x1000 |
| #define | TCR_EPH_LOOP 0x2000 |
| #define | TCR_SWFDUP 0x8000 |
| #define | TCR_DEFAULT TCR_TXENA | TCR_PAD_EN |
| #define | EPH_REG MSMC | 0x0002 |
| #define | EPH_TX_SUC 0x0001 |
| #define | EPH_SNGLCOL 0x0002 |
| #define | EPH_MULCOL 0x0004 |
| #define | EPH_LTXMULT 0x0008 |
| #define | EPH_16COL 0x0010 |
| #define | EPH_SQET 0x0020 |
| #define | EPH_LTXBRD 0x0040 |
| #define | EPH_TXDEFR 0x0080 |
| #define | EPH_LATCOL 0x0200 |
| #define | EPH_LOSTCARR 0x0400 |
| #define | EPH_EXC_DEF 0x0800 |
| #define | EPH_CTR_ROL 0x1000 |
| #define | EPH_LINK_OK 0x4000 |
| #define | EPH_TXUNRN 0x8000 |
| #define | RCR_REG MSMC | 0x0004 |
| #define | RCR_RX_ABORT 0x0001 |
| #define | RCR_PRMS 0x0002 |
| #define | RCR_ALMUL 0x0004 |
| #define | RCR_RXEN 0x0100 |
| #define | RCR_STRIPCRC 0x0200 |
| #define | RCR_ABORT_ENB 0x0200 |
| #define | RCR_FILTCAR 0x0400 |
| #define | RCR_SOFTRST 0x8000 |
| #define | RCR_DEFAULT (RCR_STRIPCRC | RCR_RXEN) |
| #define | RCR_CLEAR 0x0 |
| #define | COUNTER_REG MSMC | 0x0006 |
| #define | MIR_REG MSMC | 0x0008 |
| #define | RPC_REG MSMC | 0x000A |
| #define | RPC_SPEED 0x2000 |
| #define | RPC_DPLX 0x1000 |
| #define | RPC_ANEG 0x0800 |
| #define | RPC_LSXA_SHFT 5 |
| #define | RPC_LSXB_SHFT 2 |
| #define | RPC_LED_100_10 (0x00) |
| #define | RPC_LED_RES (0x01) |
| #define | RPC_LED_10 (0x02) |
| #define | RPC_LED_FD (0x03) |
| #define | RPC_LED_TX_RX (0x04) |
| #define | RPC_LED_100 (0x05) |
| #define | RPC_LED_TX (0x06) |
| #define | RPC_LED_RX (0x07) |
| #define | RPC_DEFAULT (RPC_ANEG | (RPC_LED_100_10 << RPC_LSXA_SHFT) | (RPC_LED_TX_RX << RPC_LSXB_SHFT)) |
| #define | BSR_REG MSMC | 0x000E |
| #define | CFG_REG MSMC | 0x0000 |
| #define | CFG_EXTPHY 0x0200 |
| #define | CFG_GPCNTRL 0x0400 |
| #define | CFG_NOWAIT 0x1000 |
| #define | CFG_EPH_POWER_EN 0x8000 |
| #define | CFG_RESERVED 0x20b1 |
| #define | BASE_REG MSMC | 0x0002 |
| #define | BASE_DEFAULT 0x1801 |
| #define | ADDR0_REG MSMC | 0x0004 |
| #define | ADDR1_REG MSMC | 0x0006 |
| #define | ADDR2_REG MSMC | 0x0008 |
| #define | GP_REG MSMC | 0x000A |
| #define | CTL_REG MSMC | 0x000C |
| #define | CTL_RCV_BAD 0x4000 |
| #define | CTL_AUTO_RELEASE 0x0800 |
| #define | CTL_LEENABLE 0x0080 |
| #define | CTL_CRENABLE 0x0040 |
| #define | CTL_TEENABLE 0x0020 |
| #define | CTL_EEPROM_SELECT 0x0004 |
| #define | CTL_RELOAD 0x0002 |
| #define | CTL_STORE 0x0001 |
| #define | MMU_CMD_REG MSMC | 0x0000 |
| #define | MC_BUSY 1 |
| #define | MC_NOP (0<<5) |
| #define | MC_ALLOC (1<<5) |
| #define | MC_RESET (2<<5) |
| #define | MC_REMOVE (3<<5) |
| #define | MC_RELEASE (4<<5) |
| #define | MC_FREEPKT (5<<5) |
| #define | MC_ENQUEUE (6<<5) |
| #define | MC_RSTTXFIFO (7<<5) |
| #define | PN_REG MSMC | 0x0002 |
| #define | AR_REG MSMC | 0x0003 |
| #define | AR_FAILED 0x80 |
| #define | FIFO_REG MSMC | 0x0004 |
| #define | RXFIFO_REMPTY 0x8000 |
| #define | TXFIFO_TEMPTY 0x0080 |
| #define | PTR_REG MSMC | 0x0006 |
| #define | PTR_RCV 0x8000 |
| #define | PTR_AUTOINC 0x4000 |
| #define | PTR_READ 0x2000 |
| #define | DATA_REG MSMC | 0x0008 |
| #define | INT_REG MSMC | 0x000C |
| #define | IM_REG MSMC | 0x000D |
| #define | IM_MDINT 0x80 |
| #define | IM_ERCV_INT 0x40 |
| #define | IM_EPH_INT 0x20 |
| #define | IM_RX_OVRN_INT 0x10 |
| #define | IM_ALLOC_INT 0x08 |
| #define | IM_TX_EMPTY_INT 0x04 |
| #define | IM_TX_INT 0x02 |
| #define | IM_RCV_INT 0x01 |
| #define | SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_MDINT) |
| #define | MCAST_REG1 MSMC | 0x0000 |
| #define | MCAST_REG2 MSMC | 0x0002 |
| #define | MCAST_REG3 MSMC | 0x0004 |
| #define | MCAST_REG4 MSMC | 0x0006 |
| #define | MII_REG MSMC | 0x0008 |
| #define | MII_MSK_CRS100 0x4000 |
| #define | MII_MDOE 0x0008 |
| #define | MII_MCLK 0x0004 |
| #define | MII_MDI 0x0002 |
| #define | MII_MDO 0x0001 |
| #define | REV_REG MSMC | 0x000A |
| #define | ERCV_REG MSMC | 0x000C |
| #define | ERCV_RCV_DISCRD 0x0080 |
| #define | ERCV_THRESHOLD 0x001F |
| #define | PHY_CNTL_REG 0x00 |
| #define | PHY_CNTL_RST 0x8000 |
| #define | PHY_CNTL_LPBK 0x4000 |
| #define | PHY_CNTL_SPEED 0x2000 |
| #define | PHY_CNTL_ANEG_EN 0x1000 |
| #define | PHY_CNTL_PDN 0x0800 |
| #define | PHY_CNTL_MII_DIS 0x0400 |
| #define | PHY_CNTL_ANEG_RST 0x0200 |
| #define | PHY_CNTL_DPLX 0x0100 |
| #define | PHY_CNTL_COLTST 0x0080 |
| #define | PHY_STAT_REG 0x01 |
| #define | PHY_STAT_CAP_T4 0x8000 |
| #define | PHY_STAT_CAP_TXF 0x4000 |
| #define | PHY_STAT_CAP_TXH 0x2000 |
| #define | PHY_STAT_CAP_TF 0x1000 |
| #define | PHY_STAT_CAP_TH 0x0800 |
| #define | PHY_STAT_CAP_SUPR 0x0040 |
| #define | PHY_STAT_ANEG_ACK 0x0020 |
| #define | PHY_STAT_REM_FLT 0x0010 |
| #define | PHY_STAT_CAP_ANEG 0x0008 |
| #define | PHY_STAT_LINK 0x0004 |
| #define | PHY_STAT_JAB 0x0002 |
| #define | PHY_STAT_EXREG 0x0001 |
| #define | PHY_ID1_REG 0x02 |
| #define | PHY_ID2_REG 0x03 |
| #define | PHY_AD_REG 0x04 |
| #define | PHY_AD_NP 0x8000 |
| #define | PHY_AD_ACK 0x4000 |
| #define | PHY_AD_RF 0x2000 |
| #define | PHY_AD_T4 0x0200 |
| #define | PHY_AD_TX_FDX 0x0100 |
| #define | PHY_AD_TX_HDX 0x0080 |
| #define | PHY_AD_10_FDX 0x0040 |
| #define | PHY_AD_10_HDX 0x0020 |
| #define | PHY_AD_CSMA 0x0001 |
| #define | PHY_RMT_REG 0x05 |
| #define | PHY_CFG1_REG 0x10 |
| #define | PHY_CFG1_LNKDIS 0x8000 |
| #define | PHY_CFG1_XMTDIS 0x4000 |
| #define | PHY_CFG1_XMTPDN 0x2000 |
| #define | PHY_CFG1_BYPSCR 0x0400 |
| #define | PHY_CFG1_UNSCDS 0x0200 |
| #define | PHY_CFG1_EQLZR 0x0100 |
| #define | PHY_CFG1_CABLE 0x0080 |
| #define | PHY_CFG1_RLVL0 0x0040 |
| #define | PHY_CFG1_TLVL_SHIFT 2 |
| #define | PHY_CFG1_TLVL_MASK 0x003C |
| #define | PHY_CFG1_TRF_MASK 0x0003 |
| #define | PHY_CFG2_REG 0x11 |
| #define | PHY_CFG2_APOLDIS 0x0020 |
| #define | PHY_CFG2_JABDIS 0x0010 |
| #define | PHY_CFG2_MREG 0x0008 |
| #define | PHY_CFG2_INTMDIO 0x0004 |
| #define | PHY_INT_REG 0x12 |
| #define | PHY_INT_INT 0x8000 |
| #define | PHY_INT_LNKFAIL 0x4000 |
| #define | PHY_INT_LOSSSYNC 0x2000 |
| #define | PHY_INT_CWRD 0x1000 |
| #define | PHY_INT_SSD 0x0800 |
| #define | PHY_INT_ESD 0x0400 |
| #define | PHY_INT_RPOL 0x0200 |
| #define | PHY_INT_JAB 0x0100 |
| #define | PHY_INT_SPDDET 0x0080 |
| #define | PHY_INT_DPLXDET 0x0040 |
| #define | PHY_MASK_REG 0x13 |
| #define | TS_SUCCESS 0x0001 |
| #define | TS_LOSTCAR 0x0400 |
| #define | TS_LATCOL 0x0200 |
| #define | TS_16COL 0x0010 |
| #define | RS_ALGNERR 0x8000 |
| #define | RS_BRODCAST 0x4000 |
| #define | RS_BADCRC 0x2000 |
| #define | RS_ODDFRAME 0x1000 |
| #define | RS_TOOLONG 0x0800 |
| #define | RS_TOOSHORT 0x0400 |
| #define | RS_MULTICAST 0x0001 |
| #define | RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
Typedefs | |
| typedef _ADI_ETHER_LAN91C111_DATA | ADI_ETHER_LAN91C111_DATA |
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1.4.1